HONG KONG, Aug.  12, 2026  (GLOBE NEWSWIRE) -- 3 E Network Technology Group Limited (NASDAQ:MASK) (the &#34;Company&#34; or &#34;3 E Network&#34;), a business-to-business (&#34;B2B&#34;) information technology

MASK

3 E Network Establishes AI Storage Controller Architecture and Validates Core Data Flow Algorithms

3 E Network advances AI storage R&D milestones; potential near-term upside for MASK

<section class="insight" data-version="1">
  <section data-block="information">
    <h3>Information</h3>
    <p>HONG KONG, Aug.  12, 2026  (GLOBE NEWSWIRE) -- 3 E Network Technology Group Limited (NASDAQ:MASK) (the &amp;#34;Company&amp;#34; or &amp;#34;3 E Network&amp;#34;), a business-to-business (&amp;#34;B2B&amp;#34;) information technology</p>
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  <section data-block="ai-summary-paragraph">
    <h3>AI Summary</h3>
    <p>3 E Network announced completion of Version 1.0 system-level architecture for the AI storage controller within its Chip Business Unit, along with software validation of a short-path data flow. The milestone targets reducing I/O bottlenecks in AI compute as models scale, signaling hardware progress that could influence MASK&#039;s valuation if sustained through further milestones.</p>
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  <section data-block="ai-summary-bullets">
    <h3>Key Points</h3>
    <ul><li>3 E Network reports CBU milestone. Completed Version 1.0 architecture spec.</li><li>Software models core data flow; short-path aims to cut latency.</li><li>AI memory bottlenecks discussed: memory wall, I/O wall, high concurrency.</li><li>Forward-looking statements caution; no near-term revenue figures provided.</li></ul>
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  <section data-block="companies-mentioned">
    <h3>Companies Mentioned</h3>
    <ul><li><strong>3 E Network Technology Group Limited (MASK)</strong>: Announced semiconductor R&amp;D milestone; progress could influence AI storage hardware roadmap and valuation; forward-looking statements warn of uncertainty.</li><li><strong>Chip Business Unit (CBU) of 3 E Network Technology Group Limited (N/A)</strong>: Internal R&amp;D division driving the milestone; potential monetization depends on future commercialization.</li></ul>
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  <section data-block="category">
    <h3>Corporate Developments</h3>
    <p>Category: Corporate Developments. The piece highlights an internal R&amp;D milestone and its potential longer-term implications for MASK&#039;s product roadmap and valuation, rather than immediate revenue or earnings factors.</p>
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  <section data-block="market-moving">
    <h3>Market-Moving</h3>
    <ul><li>Version 1.0 architecture spec completion could shift near-term expectations for MASK&#039;s AI hardware roadmap.</li><li>Software modeling success may lift sentiment around potential I/O throughput improvements.</li><li>Lack of revenue guidance may keep stock reaction muted or volatile.</li><li>AI datacenter capex cycle could amplify any positive trajectory on hardware milestones.</li></ul>
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  <section data-block="key-facts">
    <h3>Key Facts</h3>
    <ul><li>Date: Aug 12, 2026.</li><li>Company: 3 E Network Technology Group Limited (MASK).</li><li>Completed Version 1.0 system-level storage controller architecture.</li><li>Chip Business Unit led by Vice President Siyang Hu.</li><li>Software simulation validates short-path data flow model.</li></ul>
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  <section data-block="trading-thesis">
    <h3>Trading Thesis</h3>
    <p>Bullish near-term if hardware milestones translate into commercialization progress within 3–6 quarters.</p>
  </section>
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<link type="text/css" rel="stylesheet" href="https://www.globenewswire.com/styles/gnw_nitf.css"></link><p align="justify">HONG KONG, Aug.  12, 2026  (GLOBE NEWSWIRE) -- 3 E Network Technology Group Limited (NASDAQ:<a class="ticker" href="https://www.benzinga.com/quote/MASK">MASK</a>) (the "Company" or "3 E Network"), a business-to-business ("B2B") information technology ("IT") business solutions provider, committed to becoming a next-generation artificial intelligence ("AI") infrastructure solutions provider, today announced a significant milestone in its semiconductor technology R&amp;D. Following the recent official establishment of its Chip Business Unit ("CBU"), the Company announced that its next-generation customized storage controller, designed to address the concurrent data throughput demands of AI large models, has successfully completed the initial system-level architecture specification. Concurrently, the team has preliminarily validated its core data flow algorithmic through software simulation.</p>  <p align="justify">The achievement of this engineering milestone signifies that the CBU, led by Vice President Mr. Siyang Hu, is efficiently translating its strategic blueprint into tangible hardware design progress, steadily advancing its goal to alleviate the underlying Input/Output ("I/O") bottlenecks of AI compute.</p>  <p align="justify"><strong>Addressing the AI Infrastructure Bottlenecks in the Era of Large Models</strong></p>  <p align="justify">With the surging application of large language models, mixture of experts architectures, and multi-modal AI, computing infrastructure is facing structural challenges. During distributed large-scale training and inference, the overall system performance bottleneck is gradually shifting from GPU logic compute power to the read/write latency and storage bandwidth of underlying tensor data—referred to in the industry as the "Memory Wall" and "I/O Wall." Currently, AI data centers are facing the following pain points:</p>  <ul type="disc"><li style="text-align:justify;"><strong>High-concurrency and fine-grained read/write demands:</strong> The training of AI large models involves massive, high-frequency concurrent read/write operations of unstructured small files, which significantly exceeds the capabilities of traditional cloud storage architectures.</li><li style="text-align:justify;"><strong>Instruction congestion caused by traditional protocol stacks:</strong> The complex software protocol stacks and background garbage collection mechanisms of widely used general-purpose Solid State Drive controllers, based on standard block storage protocols (such as NVMe/TCP), are prone to causing instruction queue congestion when processing extreme AI task flows.</li><li style="text-align:justify;"><strong>Tail latency reducing compute efficiency:</strong> The tail latency generated by these factors easily causes expensive advanced-node GPUs to fall into a state of "Data Starvation," thereby significantly diluting the overall effective compute utilization rate of data centers.<br></br></li></ul>  <p align="justify"><strong>Core Technological Progress: Architecture Definition and Software Modeling</strong></p>  <p align="justify">To fundamentally optimize compute efficiency, the 3 E Network CBU redesigned the storage controller architecture focusing on the underlying logic of data flow efficiency. The technological progress announced today encompasses the following phased engineering milestones:</p>  <ul type="disc"><li style="text-align:justify;"><strong>Completion of the initial architecture specification: </strong>The R&amp;D team completed a Version 1.0 system-level specification for the storage controller, setting out the preliminary engineering requirements and functional parameters for the detailed circuit design phase.</li><li style="text-align:justify;"><strong>Development of high-speed bus and routing strategies: </strong>The specification sets out a proposed framework for supporting high-speed bus standards, including customized interface logic designed to support PCIe and CXL standards, and a preliminary routing strategy intended to reduce latency for the Memory Management Unit.</li><li style="text-align:justify;"><strong>Software modeling of short-path data flow: </strong>Addressing the latency issues of traditional protocol stacks, the R&amp;D team utilized high-level languages to build a system-level software simulator and successfully ran a preliminary model of a direct memory access strategy optimized for tensor data within this software environment.</li><li style="text-align:justify;"><strong>Simulation-based optimization of I/O throughput: </strong>Early software simulation data indicates that this "short-path" algorithm model, which aims to bypass redundant protocol stacks, can potentially reduce context switching overhead. In future physical silicon implementations, this design is expected to shorten instruction queue latency, potentially optimizing the overall I/O throughput performance of compute clusters.</li></ul>  <p align="justify"><strong>Management Commentary and Next Steps</strong></p>  <p align="justify">Mr. Siyang Hu, Vice President and Head of the CBU at 3 E Network, stated: "In the rigorous semiconductor development process, the system architecture definition is crucial, as it sets the foundational framework for the chip’s ultimate performance. Since the department’s inception, within a short period, our team has efficiently completed the initial architecture specification for the AI storage system and preliminarily validated the software models of our core algorithms. This demonstrates the team’s solid design capabilities and execution, proving our ability to translate strategic vision into concrete engineering practice. We remain committed to addressing the underlying I/O bottleneck issues in AI compute."</p>  <p align="justify">Dr. Tingjun Yang, Chief Executive Officer of 3 E Network, commented: "Underlying semiconductor R&amp;D requires long-term patience and systematic engineering planning. The progress announced today represents a steady and important step forward. It transparently demonstrates to the market that 3 E Network is strengthening its core technologies capabilities."</p>  <p align="justify">With the initial shaping of the system-level architectural design, the 3 E Network chip R&amp;D team has entered a more detailed micro-architecture design phase and has begun the highly complex register transfer level front-end logic coding. The Company will continue to follow the objective laws of semiconductor R&amp;D as it continues to progress toward subsequent engineering milestones.</p>  <p align="justify"><strong>About 3 E Network Technology Group Limited</strong><br></br>3 E Network Technology Group Limited is a business-to-business ("B2B") information technology ("IT") business solutions provider committed to becoming a next-generation artificial intelligence ("AI") infrastructure solutions provider. It upholds the industry consensus of "AI and energy symbiosis" and has a strong vision in the field of energy investment. The Company’s business comprises two main portfolios: the data center operation services portfolio and the software development portfolio. For more information, please visit the Company’s website at <a href="https://www.globenewswire.com/Tracker?data=EZYLMg-o5mkXAQQVQiMbWmeP0v8pWxy0Lyl6wNc8Uf7fMxkU1WLKPW0cVuhsX0IwWHn2epMflvQPQUtKzwq_cQVHKSxFzHdaNPB2PXigA6s=" rel="nofollow" target="_blank">https://3emask.com/</a>.</p>  <p align="justify"><strong>Forward-Looking Statements</strong><br></br>Certain statements in this announcement are forward-looking statements. These forward-looking statements involve known and unknown risks and uncertainties and are based on the Company’s current expectations and projections about future events that the Company believes may affect its financial condition, results of operations, business strategy, and financial needs. Investors can identify these forward-looking statements by words or phrases such as "approximates," "assesses," "believes," "hopes," "expects," "anticipates," "estimates," "projects," "intends," "plans," "will," "would," "should," "could," "may" or similar expressions. The Company undertakes no obligation to update or revise publicly any forward-looking statements to reflect subsequent events or circumstances, or changes in its expectations, except as may be required by law. Although the Company believes that the expectations expressed in these forward-looking statements are reasonable, it cannot assure you that such expectations will turn out to be correct, and the Company cautions investors that actual results may differ materially from the anticipated results and encourages investors to review other factors that may affect the Company’s future results in the Company’s registration statement and other filings with the U.S. Securities and Exchange Commission.</p>  <p align="justify"><strong>For more information, please contact:</strong></p>  <p align="justify"><strong>3 E Network Technology Group Limited</strong><br></br>Investor Relations Department<br></br>Email: <a href="https://www.globenewswire.com/Tracker?data=SsAoPK1M0pj_kN2r6VoZX4-jXFwO3Z1R3nyRqBYIEit-k6sy4Ghek_7OfgsWxJCGIxTiXJGltqGNUWmpPauRFg==" rel="nofollow" target="_blank">ird@3emask.com</a><br></br>Website: <a href="https://www.globenewswire.com/Tracker?data=EZYLMg-o5mkXAQQVQiMbWgkjJl0ExLnJH72V7dn4qJ6b5AxgZEZL8sq5lHIbCEqsbA-TEH7XMqauhcAngCkBD4Mod8S-9pl94udHs5atm7g=" rel="nofollow" target="_blank">https://3emask.com/</a></p> <img alt="" class="__GNW8366DE3E__IMG" src="https://www.globenewswire.com/newsroom/ti?nf=OTgwODUxMSM3NzcyMzAzIzIzMDU4NTM="></img> <br></br><img alt="" src="https://ml.globenewswire.com/media/MDA0NDJkM2EtNjYyNC00Yjg3LWJiMzctZDRjYzE2YzJjOGQ4LTEzMTc0MDMtMjAyNi0wOC0xMi1lbg==/tiny/3E-Network-Technology-Group-Li.png" referrerpolicy="no-referrer-when-downgrade"></img><p><a href="https://www.globenewswire.com/NewsRoom/AttachmentNg/8f4e21c2-5e2c-4ce6-88ee-66c06500e891"><img src="https://ml.globenewswire.com/media/8f4e21c2-5e2c-4ce6-88ee-66c06500e891/small/22222-2026-01-14-183954-150-jpg.jpg" border="0" width="150" height="79" alt="Primary Logo"></img></a></p>

3 E Network announced completion of Version 1.0 system-level architecture for the AI storage controller within its Chip Business Unit, along with software validation of a short-path data flow. The milestone targets reducing I/O bottlenecks in AI compute as models scale, signaling hardware progress that could influence MASK's valuation if sustained through further milestones.

News insight

3 E Network Establishes AI Storage Controller Architecture and Validates Core Data Flow Algorithms

AI summary

Sentiment rationale

Key facts

Corporate Developments